1. Field of the Invention
The embodiments generally relate to digital integrated circuit (IC) chip design, and to a method of creating and using a statistical library, i.e., a Liberty model, including delay and power values for all cells, for each of the statistical parameter corners associated with each selected input load and each selected input slew. More particularly, the delay of a single statistical corner from the statistical library may be compared with a chip sign-off statistical delay requirement of a test macro having a same statistical corner definition and a global parameter scaled to match the delay of the single statistical corner from the statistical library, including any on-chip variation, to that of the chip sign-off statistical delay requirement.
2. Description of Related Art
During digital IC chip design, the complexity of the structures included in the design grows with every sequential design phase: from chip planning, synthesis, floor planning placement, clock and test insertion, wiring, and final checks. In every design phase, it is customary to verify the design against the performance specifications for the digital IC chip. One verification process includes timing analysis, which attempts to verify that all timing constraints, e.g., delays, are met for the environmental parameters, e.g. voltage and temperature, of the digital IC chip design. In addition, timing constraints are affected by variations in process parameters, e.g., chemical mechanical polishing, optical proximity effects, random dopant effects, line-edge roughness, dose and focus variation, which introduce on-chip variations for timing constraints. Similarly, aging parameters, e.g., hot-electron transfer and negative bias temperature instability, and N/P mistrack parameters may also introduce on-chip variations for the timing constraints. Such on-chip variations are defined by distances between circuits, and thus, capture the chip topology of the IC circuit design.
Typically, digital IC chip design is facilitated by using standard cells, i.e., standard groups of transistors and interconnects that perform logic or storage functions. Each standard cell is associated with a standard cell library, which includes information related to layout, schematic, symbol, and other logical and simulation views, and timing information related to environmental parameters, such as voltage and temperature.
A library or Liberty model file may include information related to timing and power parameters associated with any standard cell in a particular semiconductor technology. The timing and power parameters may be obtained by simulating the cells under a variety of environmental and manufacturing process conditions and the data is represented in the .lib format, as is well known to those in the art.
One approach to a timing analysis that can handle variations in environmental and process parameters for a digital IC chip design includes conducting multiple static timing analyses. A static timing analysis is conducted for each “corner” of a parameter space, where a corner refers to a multi-dimensional set of discrete environmental and process parameters, for example, process-voltage-temperature (PVT), that cause variations in the static timing analysis of the digital IC chip design. Corners can include a “worst case” corner that provides the slowest path delay between two nodes in a particular circuit path, and a “best case” corner that provides a fastest path delay between the two nodes in the particular circuit path. Bounding the timing for each possible corner of the parameter space leads to a large number of timing runs, i.e., 2N runs for N parameters that take on worst case and best case values. This large number of timing runs makes it difficult to evaluate the performance limits, i.e., timing closure, for a digital IC chip design that includes a large number of parameters.
Although faster and requiring less memory, a single timing run conducted at a single corner of the parameter space can incorporate a global timing margin, i.e., a global timing scalar that is applied to all possible timing outcomes, to ensure acceptable performance outcomes. However, large global margins are needed to ensure that each timing outcome passes the worst case condition including on-chip variation (OCV) of manufacturing process parameters. Such large global margins are unduly pessimistic.
Timing outcomes can also be determined by using a statistical static timing analysis that propagates timing quantities as probabilistic statistical distributions instead of single-valued deterministic values. In statistical static timing analysis, statistical minimum and maximum operations are used to calculate timing outcomes for the propagated statistical distributions through all cells and timing paths of the digital IC chip design. As the inputs to these operations are functions of statistical distributions, the outputs of statistical minimum or maximum operations are also functions of statistical distributions. These propagated statistical distributions will typically overlap, such that each one will produce a minimum or maximum for some percentage of the time over numerous samples. Therefore, the output function is defined as a linear combination of all of the inputs, with each input weighted by the probability that it will produce either the minimum or the maximum result. Such statistical static timing analysis, however, requires the greatest amount of run time and memory because the propagated statistically distributed timing outputs are evaluated for every cell and every timing arc of the digital IC chip design across each of the range values of every one of the environmental and process parameters.
There remains a need to perform a timing and power analysis of a digital IC chip design that avoids the run time and memory requirements of a statistical static timing analysis of an entire digital IC chip design, yet utilizes the shorter run times and smaller memory requirements of deterministic static timing analyses for environmental, process, aging, and N/P mistrack parameters, and provides the lesser pessimism, associated with on-chip variation (OCV), as opposed to global margins.